日月光 Targets Initial Volume Production for AMD Venice in Q1 2027
Photo: TokenPost
Panel-level packaging for AMD’s Venice CPU targets initial volume production in Q1 2027, with output potentially limited, as Taiwan’s Ministry of Economic Affairs investment review committee approved 力成’s $400 million investment in a Singapore venture. 日月光 and its subsidiary 矽品 are working with AMD on second-generation fan-out embedded bridge (FOEB) packaging for the CPU. Initial volume production is targeted for Q1 2027, with the first run potentially limited. Panel-level packaging (PLP) uses large square panels instead of circular wafers. For Venice, the interposer is 2.7 times the size of a photomask reticle.
Source: TokenPost
